1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to a 3D integrated circuit stack-wide synchronization circuit.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as strata or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 or other technology, and the strata could include through-Silicon vias (TSVs) to connect from the active electronics on one side of the stratum to the opposite side of the stratum. The active electronics can be on the “front” or “back” side of the stratum.
In a 3D integrated stack, all strata may operate synchronously from a given clock source. For some operations, it is required that an asynchronous signal, originating outside of the stack, trigger a synchronized operation with all strata of the stack. A “strobe” and a “start” operation are examples of such operations. This synchronization must occur regardless of process or parameter or temperature or voltage variations across the stack.